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2000 Microchip Technology Inc.

DS30605C-page 39

PIC16C63A/65B/73B/74B

6.0

TIMER0 MODULE

The Timer0 module timer/counter has the following fea-

tures:

8-bit timer/counter

Readable and writable

8-bit software programmable prescaler

Internal or external clock select

Interrupt on overflow from FFh to 00h

Edge select for external clock

Figure 6-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

Additional information on the Timer0 module is

available in the PICmicro Mid-Range MCU Family

Reference Manual (DS33023).

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescaler). If the TMR0 register is written, the incre-

ment is inhibited for the following two instruction cycles.

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In counter mode, Timer0 will

increment, either on every rising, or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the

Timer0

Source

Edge

Select

bit

T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the watchdog timer. The

prescaler is not readable or writable. Section 6.3

details the operation of the prescaler.

6.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

FIGURE 6-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

CLKOUT (= FOSC/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag bit T0IF

on Overflow

PSA

T0CS

PRESCALER

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